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(parent: 83a0c34) | patch
drm/amdgpu/mes: correct register offset for sienna_cichlid
authorLikun Gao <Likun.Gao@amd.com>
Wed, 20 Nov 2019 08:21:22 +0000 (16:21 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 1 Jul 2020 05:59:09 +0000 (01:59 -0400)
commit25fc05648f49e083e3cf031626b8ecf86fca5dd1
tree6db5b0549c969e8e27fefdd2e8e06eb5b10548e8tree | snapshot
parent83a0c342e04adca17eb89a75889ee295d8b82c3ecommit | diff
drm/amdgpu/mes: correct register offset for sienna_cichlid

Correct CP_MES_IC_OP_CNTL register address for sienna_cichlid on mes v10.1.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/mes_v10_1.c diff | blob | history
ep93xx device tree rework repo: git://git.maquefel.me/linux.git