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(parent: 78cedfa) | patch
target/arm: Flush high bits of sve register after AdvSIMD TBL/TBX
authorRichard Henderson <richard.henderson@linaro.org>
Fri, 14 Feb 2020 19:46:41 +0000 (11:46 -0800)
committerPeter Maydell <peter.maydell@linaro.org>
Fri, 21 Feb 2020 16:07:00 +0000 (16:07 +0000)
commit263273bc988e677ebadeaf7d0e49f6792a112db5
tree8bcf88b6395690d81f0295043897fc57c34b00e9tree | snapshot
parent78cedfabd53b6f64e7e64fc84878d848e5df1d08commit | diff
target/arm: Flush high bits of sve register after AdvSIMD TBL/TBX

Writes to AdvSIMD registers flush the bits above 128.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200214194643.23317-3-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target/arm/translate-a64.c diff | blob | history
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