clk: renesas: r8a7794: Fix LB clock divider
authorGeert Uytterhoeven <geert+renesas@glider.be>
Thu, 29 Mar 2018 09:03:00 +0000 (11:03 +0200)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Mon, 16 Apr 2018 11:39:51 +0000 (13:39 +0200)
commit279ebbcae5a1298433c1b4f9425c89897d017cc0
treeadcf64974d36ac5011d1784b878d09ea7a64899f
parent0873305e68ac2a4665f1f3d27bb0b98a4312e5bd
clk: renesas: r8a7794: Fix LB clock divider

The CLK_TYPE_GEN2_LB clock type is meant for SoCs like R-Car H2, where
the LB clock divider depends on the value of the MD18 pin.

On R-Car E2, the LB clock divider is fixed to 24.  Hence model the clock
as a fixed factor clock instead.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
drivers/clk/renesas/r8a7794-cpg-mssr.c