drm/i915: Configure TRANS_SET_CONTEXT_LATENCY correctly on ADL+
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Mon, 13 Feb 2023 22:52:56 +0000 (00:52 +0200)
committerVille Syrjälä <ville.syrjala@linux.intel.com>
Mon, 20 Feb 2023 21:24:26 +0000 (23:24 +0200)
commit2846cf3fdb8b500e374efdcad3134633dcc5ce60
tree211da5de80f2b1fdd94d373a10d1ad57ffae2cbf
parentbfa5969e1144c8d0fbbe1a976601dcbc50549757
drm/i915: Configure TRANS_SET_CONTEXT_LATENCY correctly on ADL+

On TGL VBLANK.VBLANK_START was the mechanism by which we can
delay the pipe's internal vblank in relation to the transcoder's
vblank. On ADL+ that no longer does anything. Instead we must
now use the new TRANS_SET_CONTEXT_LATENCY register. Program it
accordingly.

And since VBLANK.VBLANK_START is no longer used by the hardware
on ADL+ let's just zero it out to make it stand out in register
dumps. Seeing the zeroed value should hopefully remind people
to check the other register instead.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230213225258.2127-11-ville.syrjala@linux.intel.com
Acked-by: Jani Nikula <jani.nikula@intel.com>
drivers/gpu/drm/i915/display/intel_display.c