clk: mediatek: Add MT8188 apmixedsys clock support
authorGarmin.Chang <Garmin.Chang@mediatek.com>
Fri, 31 Mar 2023 12:36:04 +0000 (20:36 +0800)
committerStephen Boyd <sboyd@kernel.org>
Fri, 31 Mar 2023 18:51:20 +0000 (11:51 -0700)
commit28b2bc99fa76f9a8eaf22ee40fdc2a1e65fff81c
treebf49a6b418ca0603c6bcad9070ffc1012be503af
parent1086a5310f9c9421398cd12c00f605866aad24a5
clk: mediatek: Add MT8188 apmixedsys clock support

Add MT8188 apmixedsys clock controller which provides Plls
generated from SoC 26m and ssusb clock gate control.

Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230331123621.16167-3-Garmin.Chang@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
drivers/clk/mediatek/Kconfig
drivers/clk/mediatek/Makefile
drivers/clk/mediatek/clk-mt8188-apmixedsys.c [new file with mode: 0644]