PCI: pci-bridge-emul: Update for PCIe 5.0 r1.0
authorJon Derrick <jonathan.derrick@intel.com>
Mon, 11 May 2020 16:21:16 +0000 (12:21 -0400)
committerLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Fri, 22 May 2020 11:39:35 +0000 (12:39 +0100)
commit2960865127d77bce085d349c94d49faf51517df3
treef8ff5cf7ba6af9cb9b951801d2aa0933c74014b9
parentf61959b6e240640d46b65b4dd93b3144d3895ef6
PCI: pci-bridge-emul: Update for PCIe 5.0 r1.0

Add missing bits from PCIe 4.0 and updates for PCIe 5.0 r1.0.

PCIe 4.0:
Device Status bit 6 - W1C - Emergency Power Reduction Detected
Link Control bits 15:14 - RW - DRS Signaling Control
Slot Control bit 13 - RW - Auto Slow Power Limit Disable

PCIe 5.0:
Slot Control bit 14 - RW - In-Band PD Disable

Link: https://lore.kernel.org/r/20200511162117.6674-4-jonathan.derrick@intel.com
Signed-off-by: Jon Derrick <jonathan.derrick@intel.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Rob Herring <robh@kernel.org>
drivers/pci/pci-bridge-emul.c