RISC-V: cacheflush: Initialize CBO variables on ACPI systems
authorSunil V L <sunilvl@ventanamicro.com>
Wed, 18 Oct 2023 12:40:07 +0000 (18:10 +0530)
committerPalmer Dabbelt <palmer@rivosinc.com>
Thu, 26 Oct 2023 16:40:34 +0000 (09:40 -0700)
commit2960f371f1653f6d8bc2321120eba2a14c861d4c
tree39312ac65dd2961215856574a7de694bc9f8ff41
parent9ca87564190cf0e5bb72695fb0db9947fcc47843
RISC-V: cacheflush: Initialize CBO variables on ACPI systems

Initialize the CBO variables on ACPI based systems using information in
RHCT.

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Link: https://lore.kernel.org/r/20231018124007.1306159-5-sunilvl@ventanamicro.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
arch/riscv/mm/cacheflush.c