target/riscv: Add implied rule for counter delegation extensions
authorAtish Patra <atishp@rivosinc.com>
Fri, 10 Jan 2025 08:21:38 +0000 (00:21 -0800)
committerAlistair Francis <alistair.francis@wdc.com>
Sat, 18 Jan 2025 23:44:35 +0000 (09:44 +1000)
commit2a754d6957e70889e7208f4d2d6bdb9714508c9b
tree23286cc6983b91e96c039991cd37622ea0f4987b
parent04ff272d588695a2a4c328347e767b24fa241408
target/riscv: Add implied rule for counter delegation extensions

The counter delegation/configuration extensions depend on the following
extensions.

1. Smcdeleg - To enable counter delegation from M to S
2. S[m|s]csrind - To enable indirect access CSRs

Add an implied rule so that these extensions are enabled by default
if the sscfg extension is enabled.

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-ID: <20250110-counter_delegation-v5-10-e83d797ae294@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.c