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audio: tlv320aic26: fix PLL register configuration
authorMichael Williamson <michael.williamson@criticallink.com>
Fri, 20 May 2011 14:26:06 +0000 (10:26 -0400)
committerLiam Girdwood <lrg@ti.com>
Sat, 21 May 2011 11:07:56 +0000 (12:07 +0100)
commit2aba76f014a7b56ab4fe75845c5fd57b5590acc2
tree67cd2be68adce646b25b74e6e52bb6cc4f25f6c7tree | snapshot
parent4a787a3ff3f419c23ab0a5cef677fa441356b818commit | diff
audio: tlv320aic26: fix PLL register configuration

The current PLL configuration code for the tlc320aic26 codec appears to assume a
hardcoded system clock of 12 MHz.  Use the clock value provided by the DAI_OPS
API for the calculation.

Tested using a MityDSP-L138 platform providing a 24.576 MHz clock.

Signed-off-by: Michael Williamson <michael.williamson@criticallink.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@ti.com>
sound/soc/codecs/tlv320aic26.c diff | blob | history
ep93xx device tree rework repo: git://git.maquefel.me/linux.git