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(parent: fc4aa19) | patch
drm/amdgpu: use cached ih rb control reg offsets for navi10
authorHawking Zhang <Hawking.Zhang@amd.com>
Tue, 1 Dec 2020 15:30:12 +0000 (23:30 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 23 Dec 2020 20:05:02 +0000 (15:05 -0500)
commit2d2fbf685c89865d839d5d6913ff1e765ab3d3c1
tree5744ca5de1a65c32614286482ef635d99a8b569ctree | snapshot
parentfc4aa19f55af96ee7590554199a48cc9daf58a93commit | diff
drm/amdgpu: use cached ih rb control reg offsets for navi10

all the ih rb control register offsets are cached
at the beginning of navi10 ih_sw_init.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/navi10_ih.c diff | blob | history
ep93xx device tree rework repo: git://git.maquefel.me/linux.git