RISC-V: KVM: No need to use mask when hart-index-bit is 0
authorYong-Xuan Wang <yongxuan.wang@sifive.com>
Mon, 15 Apr 2024 06:49:04 +0000 (14:49 +0800)
committerAnup Patel <anup@brainfault.org>
Fri, 31 May 2024 04:17:08 +0000 (09:47 +0530)
commit2d707b4e37f9b0c37b8b2392f91b04c5b63ea538
tree37df8d23932561926ad6acda8ebad1161a18cda8
parent1613e604df0cd359cf2a7fbd9be7a0bcfacfabd0
RISC-V: KVM: No need to use mask when hart-index-bit is 0

When the maximum hart number within groups is 1, hart-index-bit is set to
0. Consequently, there is no need to restore the hart ID from IMSIC
addresses and hart-index-bit settings. Currently, QEMU and kvmtool do not
pass correct hart-index-bit values when the maximum hart number is a
power of 2, thereby avoiding this issue. Corresponding patches for QEMU
and kvmtool will also be dispatched.

Fixes: 89d01306e34d ("RISC-V: KVM: Implement device interface for AIA irqchip")
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Link: https://lore.kernel.org/r/20240415064905.25184-1-yongxuan.wang@sifive.com
Signed-off-by: Anup Patel <anup@brainfault.org>
arch/riscv/kvm/aia_device.c