target/arm: Handle Block and Page bits for security space
authorRichard Henderson <richard.henderson@linaro.org>
Fri, 23 Jun 2023 10:15:46 +0000 (11:15 +0100)
committerPeter Maydell <peter.maydell@linaro.org>
Fri, 23 Jun 2023 10:15:46 +0000 (11:15 +0100)
commit2f1ff4e7b9f30cc73e32bcb8e85fbe80a8925db1
tree1c316220fad06081631f7e346f8a1748e2e4b666
parent26d19945944b4878fa84667487a5c4fe38df960a
target/arm: Handle Block and Page bits for security space

With Realm security state, bit 55 of a block or page descriptor during
the stage2 walk becomes the NS bit; during the stage1 walk the bit 5
NS bit is RES0.  With Root security state, bit 11 of the block or page
descriptor during the stage1 walk becomes the NSE bit.

Rather than collecting an NS bit and applying it later, compute the
output pa space from the input pa space and unconditionally assign.
This means that we no longer need to adjust the output space earlier
for the NSTable bit.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230620124418.805717-13-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target/arm/ptw.c