drm/msm/dpu: fix the programming of INTF_CFG2_DATA_HCTL_EN
authorAbhinav Kumar <quic_abhinavk@quicinc.com>
Thu, 1 Feb 2024 00:47:36 +0000 (16:47 -0800)
committerDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Sun, 11 Feb 2024 20:38:07 +0000 (22:38 +0200)
commit2f4a67a3894e15c135125cb54edc5b43abc1b70e
tree5e7214fc93cc39935c8477a408d2c2c9f69809e4
parent6215f1558babad58e9797931a70272718fb77eff
drm/msm/dpu: fix the programming of INTF_CFG2_DATA_HCTL_EN

Currently INTF_CFG2_DATA_HCTL_EN is coupled with the enablement
of widebus but this is incorrect because we should be enabling
this bit independent of widebus except for cases where compression
is enabled in one pixel per clock mode.

Fix this by making the condition checks more explicit and enabling
INTF_CFG2_DATA_HCTL_EN for all other cases when supported by DPU.

Fixes: 3309a7563971 ("drm/msm/dpu: revise timing engine programming to support widebus feature")
Suggested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/576722/
Link: https://lore.kernel.org/r/20240201004737.2478-1-quic_abhinavk@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h