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(parent: 197bd23) | patch
RISC-V: KVM: add 'vlenb' Vector CSR
authorDaniel Henrique Barboza <dbarboza@ventanamicro.com>
Tue, 5 Dec 2023 17:45:08 +0000 (14:45 -0300)
committerAnup Patel <anup@brainfault.org>
Fri, 29 Dec 2023 07:01:54 +0000 (12:31 +0530)
commit2fa290372dfe7dd248b1c16f943f273a3e674f22
treeee0c9a875e4f85426d8af9c478cf72fcc622fd15tree | snapshot
parent197bd237b67268651ac544e8fedbe1fd275d41e0commit | diff
RISC-V: KVM: add 'vlenb' Vector CSR

Userspace requires 'vlenb' to be able to encode it in reg ID. Otherwise
it is not possible to retrieve any vector reg since we're returning
EINVAL if reg_size isn't vlenb (see kvm_riscv_vcpu_vreg_addr()).

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Anup Patel <anup@brainfault.org>
arch/riscv/kvm/vcpu_vector.c diff | blob | history
ep93xx device tree rework repo: git://git.maquefel.me/linux.git