target/i386: Enable support for XSAVES based features
authorYang Weijiang <weijiang.yang@intel.com>
Tue, 15 Feb 2022 19:52:54 +0000 (14:52 -0500)
committerPaolo Bonzini <pbonzini@redhat.com>
Sat, 14 May 2022 10:32:41 +0000 (12:32 +0200)
commit301e90675c3fed6cdc48682021a1ab42bc0e0d76
tree6297ef89365a2456042a1d3feeb9092fc711ccf1
parent5a778a5f820fdd907b95e93560637a61f6ea3c71
target/i386: Enable support for XSAVES based features

There're some new features, including Arch LBR, depending
on XSAVES/XRSTORS support, the new instructions will
save/restore data based on feature bits enabled in XCR0 | XSS.
This patch adds the basic support for related CPUID enumeration
and meanwhile changes the name from FEAT_XSAVE_COMP_{LO|HI} to
FEAT_XSAVE_XCR0_{LO|HI} to differentiate clearly the feature
bits in XCR0 and those in XSS.

Signed-off-by: Yang Weijiang <weijiang.yang@intel.com>
Message-Id: <20220215195258.29149-5-weijiang.yang@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
target/i386/cpu.c
target/i386/cpu.h