target/riscv: rvv-1.0: allow load element with sign-extended
authorFrank Chang <frank.chang@sifive.com>
Fri, 10 Dec 2021 07:56:20 +0000 (15:56 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Mon, 20 Dec 2021 04:51:36 +0000 (14:51 +1000)
commit308ee805786a18f236daead36b11f53cd5017899
treefb4209d390eddc8afbf1c4058bf8153a5b3d942c
parentf4f47e04de6185ddaf36e9b6ec34aa6e28923a07
target/riscv: rvv-1.0: allow load element with sign-extended

For some vector instructions (e.g. vmv.s.x), the element is loaded with
sign-extended.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-35-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/insn_trans/trans_rvv.c.inc