drm/amd/display: Enforce DPCD Address ranges
authorWesley Chalmers <Wesley.Chalmers@amd.com>
Thu, 1 Apr 2021 16:23:06 +0000 (12:23 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 15 Jun 2021 21:25:41 +0000 (17:25 -0400)
commit30adeee52d1ebadd8e4e594a54c7cf77250b91db
treef4378d55155ea19356cb5f8c4036cfae9df33a31
parent788797c793788415426ef7249ca81c66bbfb9f14
drm/amd/display: Enforce DPCD Address ranges

[WHY]
Some DPCD addresses, notably LTTPR Capability registers, are expected to
be read all together in a single DPCD transaction. Rather than force callers to
read registers they don't need, we want to quietly extend the addresses
read, and only return back the values the caller asked for.
This does not affect DPCD writes.

[HOW]
Create an additional layer above AUX to perform 'checked' DPCD
transactions.
Iterate through an array of DPCD address ranges that are marked as being
contiguous. If a requested read falls within one of those ranges, extend
the read to include the entire range.
After DPCD has been queried, copy the requested bytes into the caller's
data buffer, and deallocate all resources used.

Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/Makefile
drivers/gpu/drm/amd/display/dc/core/dc_link.c
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
drivers/gpu/drm/amd/display/dc/core/dc_link_dpcd.c [new file with mode: 0644]
drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c
drivers/gpu/drm/amd/display/dc/inc/link_dpcd.h [new file with mode: 0644]
drivers/gpu/drm/amd/display/dc/inc/link_hwss.h