target/riscv: Add Smrnmi mnret instruction
authorTommy Wu <tommy.wu@sifive.com>
Mon, 6 Jan 2025 05:43:34 +0000 (13:43 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Sat, 18 Jan 2025 23:44:34 +0000 (09:44 +1000)
commit3157a553ec6b9a52ad0aa6b52cca27d3a964167e
tree9603b79a53573457495ed64545590f6c4e2036d8
parentc1149f69ab711bf6ccdc1da492f5be47f1ebf67e
target/riscv: Add Smrnmi mnret instruction

This patch adds a new instruction 'mnret'. 'mnret' is an M-mode-only
instruction that uses the values in `mnepc` and `mnstatus` to return to the
program counter, privilege mode, and virtualization mode of the
interrupted context.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Tommy Wu <tommy.wu@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20250106054336.1878291-5-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/helper.h
target/riscv/insn32.decode
target/riscv/insn_trans/trans_privileged.c.inc
target/riscv/op_helper.c