RISC-V: Adding XTheadCondMov ISA extension
authorChristoph Müllner <christoph.muellner@vrull.eu>
Tue, 31 Jan 2023 20:20:05 +0000 (21:20 +0100)
committerAlistair Francis <alistair.francis@wdc.com>
Mon, 6 Feb 2023 22:19:23 +0000 (08:19 +1000)
commit3290933853c2c8a4a50a990cc395471097f0a173
tree7071c8681f3da94cc89a295e4dfe7c7e4ef87bc3
parentfa134585462897fc70a01d7b585fbc60371a7d17
RISC-V: Adding XTheadCondMov ISA extension

This patch adds support for the XTheadCondMov ISA extension.
The patch uses the T-Head specific decoder and translation.

Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230131202013.2541053-7-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.c
target/riscv/cpu.h
target/riscv/insn_trans/trans_xthead.c.inc
target/riscv/translate.c
target/riscv/xthead.decode