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(parent: 8a2aca3) | patch
target/riscv: Convert the RISC-V exceptions to an enum
authorAlistair Francis <alistair.francis@wdc.com>
Thu, 1 Apr 2021 15:17:29 +0000 (11:17 -0400)
committerAlistair Francis <alistair.francis@wdc.com>
Tue, 11 May 2021 10:02:06 +0000 (20:02 +1000)
commit330d2ae32af9a278bc8aa88d598f7750ff27f3dd
treeba139a94e8a4b885d7178630b8f6a64f044b1c81tree | snapshot
parent8a2aca3d79f8719b9cf79fdcdfbb89bc6bdb522acommit | diff
target/riscv: Convert the RISC-V exceptions to an enum

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: f191dcf08bf413a822e743a7c7f824d68879a527.1617290165.git.alistair.francis@wdc.com
target/riscv/cpu.c diff | blob | history
target/riscv/cpu_bits.h diff | blob | history
target/riscv/cpu_helper.c diff | blob | history
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