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(parent: 263273b) | patch
target/arm: Flush high bits of sve register after AdvSIMD ZIP/UZP/TRN
authorRichard Henderson <richard.henderson@linaro.org>
Fri, 14 Feb 2020 19:46:42 +0000 (11:46 -0800)
committerPeter Maydell <peter.maydell@linaro.org>
Fri, 21 Feb 2020 16:07:00 +0000 (16:07 +0000)
commit33649de62e40df0060a1c514574e4ef25c4e52e1
tree2a72c0d4034ff1791740617dd1e33da064a94bcetree | snapshot
parent263273bc988e677ebadeaf7d0e49f6792a112db5commit | diff
target/arm: Flush high bits of sve register after AdvSIMD ZIP/UZP/TRN

Writes to AdvSIMD registers flush the bits above 128.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200214194643.23317-4-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target/arm/translate-a64.c diff | blob | history
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