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(parent: 6b5c8eb) | patch
target/riscv: rvv-1.0: add vsetivli instruction
authorFrank Chang <frank.chang@sifive.com>
Fri, 10 Dec 2021 07:56:58 +0000 (15:56 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Mon, 20 Dec 2021 04:53:31 +0000 (14:53 +1000)
commit34a2c2d81ad94ff910051b8b93b4aaff895cec88
tree41f0d46a533da1f02b9d33e7d25768e820ae72b5tree | snapshot
parent6b5c8eb3e7de3c1b9dc2845b6b001ddd7d2eb359commit | diff
target/riscv: rvv-1.0: add vsetivli instruction

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-73-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/insn32.decode diff | blob | history
target/riscv/insn_trans/trans_rvv.c.inc diff | blob | history
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