drm/i915/adlp+: Add DSC early pixel count scaling WA (Wa_1409098942)
authorImre Deak <imre.deak@intel.com>
Mon, 29 Jan 2024 17:55:31 +0000 (19:55 +0200)
committerImre Deak <imre.deak@intel.com>
Wed, 10 Apr 2024 16:27:01 +0000 (19:27 +0300)
commit377cc98b451d049bf3d965fb414d9210a0e5959f
treecbabafa30df31fdf24d6ee899237dccd2a1db1af
parentd4e745ba81c335118c3ec5860c8b73381de2a7a9
drm/i915/adlp+: Add DSC early pixel count scaling WA (Wa_1409098942)

Add a workaround to fix timing issues on links with DSC enabled -
presumedly related to the audio functionality.

Bspec requires enabling this workaround if audio is enabled on ADLP,
however Windows enables it whenever DSC is enabled ADLP onwards; follow
Windows.

Bspec: 50490, 55424

v2: Fix WA code comment formatting. (Ankit)

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240129175533.904590-5-imre.deak@intel.com
drivers/gpu/drm/i915/display/intel_display.c
drivers/gpu/drm/i915/i915_reg.h