crypto: qat - enable dc chaining service
authorAdam Guerin <adam.guerin@intel.com>
Thu, 14 Sep 2023 14:14:13 +0000 (15:14 +0100)
committerHerbert Xu <herbert@gondor.apana.org.au>
Wed, 20 Sep 2023 05:15:54 +0000 (13:15 +0800)
commit37b14f2dfa791fd485dbc536f8d1ffe8c6990290
tree3a730c61964d38a689c6e3d6d22b9ad61c08e104
parent71713766380712c8ab2d604605e7b0b20f977801
crypto: qat - enable dc chaining service

QAT GEN4 devices support chained compression operations. These
allow, with a single request to firmware, to hash then compress
data.

Extend the configuration to enable such mode. The cfg_services
operations in sysfs are extended to allow the string "dcc". When
selected, the driver downloads to the device both the symmetric
crypto and the compression firmware images and sends an admin message
to firmware which enables `chained` operations.
In addition, it sets the device's capabilities as the combination
of compression and symmetric crypto capabilities, while excluding
the ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC bit to indicate
that in this mode, symmetric crypto instances are not supported.

When "dcc" is enabled, the device will handle compression requests
as if the "dc" configuration is loaded ("dcc" is a variation of "dc")
and the driver will register the acomp algorithms.

As for the other extended configurations, "dcc" is only available for
qat_4xxx devices and the chaining service will be only accessible from
user space.

Signed-off-by: Adam Guerin <adam.guerin@intel.com>
Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Documentation/ABI/testing/sysfs-driver-qat
drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c
drivers/crypto/intel/qat/qat_4xxx/adf_drv.c
drivers/crypto/intel/qat/qat_common/adf_admin.c
drivers/crypto/intel/qat/qat_common/adf_cfg_services.h
drivers/crypto/intel/qat/qat_common/adf_cfg_strings.h
drivers/crypto/intel/qat/qat_common/icp_qat_fw_init_admin.h