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(parent: 801faee) | patch
target/riscv/cpu.h: spelling fix: separatly
authorMichael Tokarev <mjt@tls.msk.ru>
Tue, 14 Nov 2023 16:11:33 +0000 (19:11 +0300)
committerMichael Tokarev <mjt@tls.msk.ru>
Wed, 15 Nov 2023 09:06:05 +0000 (12:06 +0300)
commit3a4e56015b897a5502ab6a691cd4e20700e779c1
tree92657ea61d7ff7c06eb8132b7dd2eb71618ed6c6tree | snapshot
parent801faee4dd15ee395fe1c2fb35241c3c7a0b9af5commit | diff
target/riscv/cpu.h: spelling fix: separatly

Fixes: 40336d5b1d4c "target/riscv: Add HS-mode virtual interrupt and IRQ filtering support."
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
target/riscv/cpu.h diff | blob | history
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