arm: dts: socfpga: Add clk-phase-sd-hs property to the sdmmc node
authorDinh Nguyen <dinguyen@kernel.org>
Mon, 3 Oct 2022 18:26:50 +0000 (13:26 -0500)
committerDinh Nguyen <dinguyen@kernel.org>
Fri, 18 Nov 2022 17:13:49 +0000 (11:13 -0600)
commit3b500ff37ce3ef5d7fbb731d082ef8f4cddce0f1
treed71c942c03f064862d41b4867041a98d1e30a3cb
parent63fb606a59a4e51572b2f34589b4afd00536f185
arm: dts: socfpga: Add clk-phase-sd-hs property to the sdmmc node

The sdmmc controller's CIU(Card Interface Unit) clock's phase can be
adjusted through the register in the system manager. Add the binding
"altr,sysmgr-syscon" to the SDMMC node for the driver to access the
system manager. Add the "clk-phase-sd-hs" property in the SDMMC node to
designate the smpsel and drvsel properties for the CIU clock.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
arch/arm/boot/dts/socfpga.dtsi
arch/arm/boot/dts/socfpga_arria10.dtsi
arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi
arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts
arch/arm/boot/dts/socfpga_arria5.dtsi
arch/arm/boot/dts/socfpga_cyclone5.dtsi
arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi