git.maquefel.me Git - linux.git/commit

author	Guo Ren <guoren@linux.alibaba.com>
	Thu, 24 Dec 2020 05:59:57 +0000 (05:59 +0000)
committer	Guo Ren <guoren@linux.alibaba.com>
	Tue, 12 Jan 2021 01:52:41 +0000 (09:52 +0800)
commit	3b756ccddb8a75563900cd603c83160b43f3d691
tree	af6428140af2760616d577a0b1e515a45b58207c	tree \| snapshot
parent	c109f42450ec25283169dd6c0acce8d053493732	commit \| diff

csky: Fix TLB maintenance synchronization problem

TLB invalidate didn't contain a barrier operation in csky cpu and
we need to prevent previous PTW response after TLB invalidation
instruction. Of cause, the ASID changing also needs to take care
of the issue.

CPU0                    CPU1
===============         ===============
set_pte
sync_is()        ->     See the previous set_pte for all harts
tlbi.vas         ->     Invalidate all harts TLB entry & flush pipeline

Signed-off-by: Guo Ren <guoren@linux.alibaba.com>

arch/csky/abiv1/inc/abi/ckmmu.h		diff \| blob \| history
arch/csky/abiv2/inc/abi/ckmmu.h		diff \| blob \| history
arch/csky/include/asm/mmu_context.h		diff \| blob \| history
arch/csky/mm/init.c		diff \| blob \| history
arch/csky/mm/tlb.c		diff \| blob \| history