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intc/arm_gic: Implement GICD_ISACTIVERn and GICD_ICACTIVERn registers
authorLuc Michel <luc.michel@greensocs.com>
Tue, 14 Aug 2018 16:17:19 +0000 (17:17 +0100)
committerPeter Maydell <peter.maydell@linaro.org>
Tue, 14 Aug 2018 16:17:19 +0000 (17:17 +0100)
commit3bb0b03897abb634231366ce4e6651b56f16aa26
tree3add5315c37b2029e5dae5b33783e4f8b27ca40ctree | snapshot
parent67ce697ac84bd7f44348830df43f05195d5987e6commit | diff
intc/arm_gic: Implement GICD_ISACTIVERn and GICD_ICACTIVERn registers

Implement GICD_ISACTIVERn and GICD_ICACTIVERn registers in the GICv2.
Those registers allow to set or clear the active state of an IRQ in the
distributor.

Signed-off-by: Luc Michel <luc.michel@greensocs.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20180727095421.386-3-luc.michel@greensocs.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
hw/intc/arm_gic.c diff | blob | history
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