target/riscv: Add Zc extension implied rule
authorFrank Chang <frank.chang@sifive.com>
Tue, 25 Jun 2024 11:46:28 +0000 (19:46 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Wed, 26 Jun 2024 13:12:21 +0000 (23:12 +1000)
commit3dd2168c33dbfebe40e964dc0d9eb445011797d6
tree7d10f9edee9e278cc08b8ddfedd91669bd31597b
parent340c3ca5f26591578171a7e6f3b6b9512fae2232
target/riscv: Add Zc extension implied rule

Zc extension has special implied rules that need to be handled separately.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com>
Tested-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240625114629.27793-6-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/tcg/tcg-cpu.c