riscv: dts: starfive: jh7110: Add PLL clocks source in SYSCRG node
authorXingyu Wu <xingyu.wu@starfivetech.com>
Mon, 17 Jul 2023 02:30:40 +0000 (10:30 +0800)
committerConor Dooley <conor.dooley@microchip.com>
Thu, 20 Jul 2023 16:22:30 +0000 (17:22 +0100)
commit3e6670a28b009cc381b40ee26a6f41509aca46eb
tree452792bdd82c09844dc1d0d726118239d012e6a3
parent3fcbcfc496f0cc08f9dc004a92915ce1cfb7ea95
riscv: dts: starfive: jh7110: Add PLL clocks source in SYSCRG node

Add PLL clocks input from PLL clocks driver in SYSCRG node.

Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
arch/riscv/boot/dts/starfive/jh7110.dtsi