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(parent: 104e548) | patch
drm/msm/a7xx: allow writing to CP_BV counter selection registers
authorZan Dobersek <zdobersek@igalia.com>
Thu, 29 Feb 2024 07:49:11 +0000 (08:49 +0100)
committerRob Clark <robdclark@chromium.org>
Sat, 4 May 2024 16:41:32 +0000 (09:41 -0700)
commit3f9bb601a10dbe3a9b506d9856708a67308bb860
tree265a571037ac6f40abc36320f2d356063fca09ebtree | snapshot
parent104e548a7c97da24224b375632fca0fc8b64c0dbcommit | diff
drm/msm/a7xx: allow writing to CP_BV counter selection registers

In addition to the CP_PERFCTR_CP_SEL register range, allow writes to the
CP_BV_PERFCTR_CP_SEL registers in the 0x8e0-0x8e6 range for profiling
purposes of tools like fdperf and perfetto.

Signed-off-by: Zan Dobersek <zdobersek@igalia.com>
Patchwork: https://patchwork.freedesktop.org/patch/580548/
[fixup a730_protect size]
Signed-off-by: Rob Clark <robdclark@chromium.org>
drivers/gpu/drm/msm/adreno/a6xx_gpu.c diff | blob | history
ep93xx device tree rework repo: git://git.maquefel.me/linux.git