bus: ti-sysc: Assert reset only after disabling clocks

bus: ti-sysc: Assert reset only after disabling clocks

The rstctrl reset must be asserted after gating the module clock as
described in the TRM at least for IVA. Otherwise the rstctrl reset
done with module clock enabled can hang the system.

Note that this issue is has been only seen with related IVA changes
that we do not currently have merged. So probably no need to apply
this patch as a fix.

Signed-off-by: Tony Lindgren <tony@atomide.com>