clk: tegra: Fix PLLM programming on Tegra124+ when PMC overrides divider
authorDmitry Osipenko <digetx@gmail.com>
Thu, 11 Apr 2019 21:48:34 +0000 (00:48 +0300)
committerStephen Boyd <sboyd@kernel.org>
Thu, 25 Apr 2019 15:17:07 +0000 (08:17 -0700)
commit40db569d6769ffa3864fd1b89616b1a7323568a8
tree9aa96c3dce3cb3ae8b56c71df77f0f6f5e3a10c3
parentbff1cef5f23afbe49f5ebd766980dc612f5e9d0a
clk: tegra: Fix PLLM programming on Tegra124+ when PMC overrides divider

There are wrongly set parenthesis in the code that are resulting in a
wrong configuration being programmed for PLLM. The original fix was made
by Danny Huang in the downstream kernel. The patch was tested on Nyan Big
Tegra124 chromebook, PLLM rate changing works correctly now and system
doesn't lock up after changing the PLLM rate due to EMC scaling.

Cc: <stable@vger.kernel.org>
Tested-by: Steev Klimaszewski <steev@kali.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
drivers/clk/tegra/clk-pll.c