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(parent: f305bf9) | patch
target/arm: Add ID_AA64SMFR0_EL1
authorRichard Henderson <richard.henderson@linaro.org>
Wed, 8 Jun 2022 18:38:59 +0000 (19:38 +0100)
committerPeter Maydell <peter.maydell@linaro.org>
Wed, 8 Jun 2022 18:38:59 +0000 (19:38 +0100)
commit414c54d515dba16bfaef643a8acec200c05f229a
tree7e67548bc1de794e33dbee7ae802b23f3f953b5ctree | snapshot
parentf305bf9436896b4cd9ef622034e166b024780874commit | diff
target/arm: Add ID_AA64SMFR0_EL1

This register is allocated from the existing block of id registers,
so it is already RES0 for cpus that do not implement SME.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220607203306.657998-21-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target/arm/cpu.h diff | blob | history
target/arm/helper.c diff | blob | history
target/arm/kvm64.c diff | blob | history
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