spi: s3c64xx: retrieve the FIFO depth from the device tree
authorTudor Ambarus <tudor.ambarus@linaro.org>
Fri, 16 Feb 2024 07:05:48 +0000 (07:05 +0000)
committerMark Brown <broonie@kernel.org>
Tue, 5 Mar 2024 20:42:53 +0000 (20:42 +0000)
commit414d7b8c9147db7dc34c0e2bae2e2361b922dc07
tree50aa9f5f598e0b0c7f1ddc5edd48b4de0bbbbcbd
parentc6e776ab6abdfce5a1edcde7a22c639e76499939
spi: s3c64xx: retrieve the FIFO depth from the device tree

There are SoCs that configure different FIFO depths for their instances
of the SPI IP. See the fifo_lvl_mask defined for exynos4_spi_port_config
for example:
        .fifo_lvl_mask  = { 0x1ff, 0x7F, 0x7F },
The first instance of the IP is configured with 256 bytes FIFOs, whereas
the last two are configured with 64 bytes FIFOs.

Instead of mangling with the .fifo_lvl_mask and its dependency of the DT
alias ID, allow such SoCs to determine the FIFO depth via the
``fifo-depth`` DT property.

Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Link: https://msgid.link/r/20240216070555.2483977-6-tudor.ambarus@linaro.org
Signed-off-by: Mark Brown <broonie@kernel.org>
drivers/spi/spi-s3c64xx.c