mlxsw: Support CQEv2 for SDQ in Spectrum-2 and newer ASICs
authorDanielle Ratson <danieller@nvidia.com>
Wed, 27 Jul 2022 06:23:21 +0000 (09:23 +0300)
committerDavid S. Miller <davem@davemloft.net>
Fri, 29 Jul 2022 10:02:23 +0000 (11:02 +0100)
commit42823208b946d85d20a7065a1b2ef6e35a7be3a9
treea0ddb469540b07b95840f291c8775b074948f18a
parent37b62b282b182acd2113f97c1b9fd651d4211027
mlxsw: Support CQEv2 for SDQ in Spectrum-2 and newer ASICs

Currently, Tx completions are reported using Completion Queue Element
version 1 (CQEv1). These elements do not contain the Tx time stamp,
which is fine as Spectrum-1 reads Tx time stamps via a dedicated FIFO
and Spectrum-2 does not currently support PTP.

In preparation for Spectrum-2 PTP support, use CQEv2 for Spectrum-2 and
newer ASICs, as this CQE format encodes the Tx time stamp.

Signed-off-by: Danielle Ratson <danieller@nvidia.com>
Signed-off-by: Amit Cohen <amcohen@nvidia.com>
Reviewed-by: Petr Machata <petrm@nvidia.com>
Signed-off-by: Ido Schimmel <idosch@nvidia.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/mellanox/mlxsw/core.c
drivers/net/ethernet/mellanox/mlxsw/core.h
drivers/net/ethernet/mellanox/mlxsw/pci.c
drivers/net/ethernet/mellanox/mlxsw/spectrum.c