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(parent: 2f42c5a) | patch
drm/i915/mtl: Update cache coherency setting for context structure
authorZhanjun Dong <zhanjun.dong@intel.com>
Thu, 6 Jul 2023 17:47:04 +0000 (10:47 -0700)
committerDaniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Wed, 12 Jul 2023 16:27:43 +0000 (09:27 -0700)
commit43aa755eae2cda71684f3f5fe40c00f728d25722
tree075846e68cb80f7bfc8a0e6f2a224241e7b51321tree | snapshot
parent2f42c5afb34b5696cf5fe79e744f99be9b218798commit | diff
drm/i915/mtl: Update cache coherency setting for context structure

As context structure is shared memory for CPU/GPU, Wa_22016122933 is
needed for this memory block as well.

Signed-off-by: Zhanjun Dong <zhanjun.dong@intel.com>
CC: Fei Yang <fei.yang@intel.com>
Reviewed-by: Fei Yang <fei.yang@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230706174704.177929-1-zhanjun.dong@intel.com
drivers/gpu/drm/i915/gt/intel_lrc.c diff | blob | history
ep93xx device tree rework repo: git://git.maquefel.me/linux.git