RISC-V: Allow both Zmmul and M
authorPalmer Dabbelt <palmer@rivosinc.com>
Thu, 14 Jul 2022 18:00:33 +0000 (11:00 -0700)
committerAlistair Francis <alistair.francis@wdc.com>
Wed, 27 Jul 2022 07:34:02 +0000 (17:34 +1000)
commit44602af8585fd2f331c69e2c071eff39227535ed
treefd0b285cf73a5acb62fa67c411fa304df2baa95a
parent7b17a1a841fc2336eba53afade9cadb14bd3dd9a
RISC-V: Allow both Zmmul and M

We got to talking about how Zmmul and M interact with each other
https://github.com/riscv/riscv-isa-manual/issues/869 , and it turns out
that QEMU's behavior is slightly wrong: having Zmmul and M is a legal
combination, it just means that the multiplication instructions are
supported even when M is disabled at runtime via misa.

This just stops overriding M from Zmmul, with that the other checks for
the multiplication instructions work as per the ISA.

Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220714180033.22385-1-palmer@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.c