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clk: samsung: exynos5420: Add SET_RATE_PARENT flag to clocks on G3D path
authorMarek Szyprowski <m.szyprowski@samsung.com>
Fri, 25 Oct 2019 09:34:35 +0000 (11:34 +0200)
committerSylwester Nawrocki <s.nawrocki@samsung.com>
Tue, 29 Oct 2019 13:57:22 +0000 (14:57 +0100)
commit45f10dabb56bc5dee52df47dccd3bfab1e58eea1
tree785cab6109225be5769e8d9719fa10b4a7df6e88tree | snapshot
parente21be0d1d7bd7f78a77613f6bcb6965e72b22fc1commit | diff
clk: samsung: exynos5420: Add SET_RATE_PARENT flag to clocks on G3D path

Add CLK_SET_RATE_PARENT flag to all clocks on the path from VPLL to G3D,
so the G3D MALI driver can simply adjust the rate of its clock by doing
a single clk_set_rate() call, without the need to know the whole clock
topology in Exynos542x SoCs.

Suggested-by: Marian Mihailescu <mihailescu2m@gmail.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
drivers/clk/samsung/clk-exynos5420.c diff | blob | history
ep93xx device tree rework repo: git://git.maquefel.me/linux.git