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target/loongarch: Fix the meaning of ECFG reg's VS field
authorXiaojuan Yang <yangxiaojuan@loongson.cn>
Fri, 1 Jul 2022 09:34:04 +0000 (17:34 +0800)
committerRichard Henderson <richard.henderson@linaro.org>
Mon, 4 Jul 2022 05:38:58 +0000 (11:08 +0530)
commit4623367697ebb531fce89a10f9c73a820a5ad82a
treeb2319dd46f0d9d3e346007ec9f995e0e9553138etree | snapshot
parent59e52dcff7254603f3b5bf527806a830f016bf82commit | diff
target/loongarch: Fix the meaning of ECFG reg's VS field

By the manual of LoongArch CSR, the VS field(18:16 bits) of
ECFG reg means that the number of instructions between each
exception entry is 2^VS.

Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220701093407.2150607-9-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
target/loongarch/cpu.c diff | blob | history
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