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(parent: 91993c8) | patch
openrisc: add 1 and 2 byte cmpxchg support
authorStafford Horne <shorne@gmail.com>
Thu, 23 Mar 2017 14:27:12 +0000 (23:27 +0900)
committerStafford Horne <shorne@gmail.com>
Fri, 3 Nov 2017 05:01:12 +0000 (14:01 +0900)
commit489e0f802db708c69004f64d92a3e1b70731614a
tree73f0b4010d05cad70a4bb60ac251f6222783b750tree | snapshot
parent91993c8c2ed52781a0f42bf7f40e28adc96e2bb2commit | diff
openrisc: add 1 and 2 byte cmpxchg support

OpenRISC only supports hardware instructions that perform 4 byte atomic
operations.  For enabling qrwlocks for upcoming SMP support 1 and 2 byte
implementations are needed.  To do this we leverage the 4 byte atomic
operations and shift/mask the 1 and 2 byte areas as needed.

This heavily borrows ideas and routines from sh and mips, which do
something similar.

Cc: Peter Zijlstra <peterz@infradead.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
arch/openrisc/include/asm/cmpxchg.h diff | blob | history
ep93xx device tree rework repo: git://git.maquefel.me/linux.git