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hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004
authorBin Meng <bin.meng@windriver.com>
Tue, 16 Jun 2020 00:50:38 +0000 (17:50 -0700)
committerAlistair Francis <alistair.francis@wdc.com>
Fri, 19 Jun 2020 15:25:27 +0000 (08:25 -0700)
commit495134b75cca3e6a34d4233113c5143439061771
tree48a0fbb22149134b29b7a7345c4a3a63b169accftree | snapshot
parente8905c6ce86f5023f6814abd7c72a809e5d018eccommit | diff
hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004

Per the SiFive manual, all E/U series CPU cores' reset vector is
at 0x1004. Update our codes to match the hardware.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1592268641-7478-3-git-send-email-bmeng.cn@gmail.com
Message-Id: <1592268641-7478-3-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
hw/riscv/sifive_e.c diff | blob | history
hw/riscv/sifive_u.c diff | blob | history
target/riscv/cpu.c diff | blob | history
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