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dt-bindings: riscv: cpus: Add AMD MicroBlaze V compatible
authorMichal Simek <michal.simek@amd.com>
Mon, 6 Nov 2023 11:37:47 +0000 (12:37 +0100)
committerPalmer Dabbelt <palmer@rivosinc.com>
Wed, 20 Dec 2023 15:15:00 +0000 (07:15 -0800)
commit4a6b93f5629668d1dc8fa5945657fdd124629c55
treea8c66e1e3b2a4e68dc654cb9df3d540793115a0atree | snapshot
parentf352a28cc2fb4ee8d08c6a6362c9a861fcc84236commit | diff
dt-bindings: riscv: cpus: Add AMD MicroBlaze V compatible

MicroBlaze V is new AMD/Xilinx soft-core 32bit RISC-V processor IP.
It is hardware compatible with classic MicroBlaze processor.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/d442d916204d26f82c1c3a924a4cdfb117960e1b.1699270661.git.michal.simek@amd.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Documentation/devicetree/bindings/riscv/cpus.yaml diff | blob | history
ep93xx device tree rework repo: git://git.maquefel.me/linux.git