target/arm: Correctly propagate stage 1 BTI guarded bit in a two-stage walk
authorPeter Maydell <peter.maydell@linaro.org>
Tue, 31 Oct 2023 17:37:23 +0000 (17:37 +0000)
committerPeter Maydell <peter.maydell@linaro.org>
Thu, 2 Nov 2023 13:36:45 +0000 (13:36 +0000)
commit4c09abeae8704970ff03bf2196973f6bf08ab6f9
tree8da7f925f6ba8278499b8ccf25ed24e2e10e3238
parente9f30b1e7f9e25e73f626596620778b2561f0c2e
target/arm: Correctly propagate stage 1 BTI guarded bit in a two-stage walk

In a two-stage translation, the result of the BTI guarded bit should
be the guarded bit from the first stage of translation, as there is
no BTI guard information in stage two.  Our code tried to do this,
but got it wrong, because we currently have two fields where the GP
bit information might live (ARMCacheAttrs::guarded and
CPUTLBEntryFull::extra::arm::guarded), and we were storing the GP bit
in the latter during the stage 1 walk but trying to copy the former
in combine_cacheattrs().

Remove the duplicated storage, and always use the field in
CPUTLBEntryFull; correctly propagate the stage 1 value to the output
in get_phys_addr_twostage().

Note for stable backports: in v8.0 and earlier the field is named
result->f.guarded, not result->f.extra.arm.guarded.

Cc: qemu-stable@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1950
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20231031173723.26582-1-peter.maydell@linaro.org
target/arm/internals.h
target/arm/ptw.c