drm/xe/uc: Use u64 for offsets for which we use upper_32_bits()
authorDaniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Tue, 19 Mar 2024 19:51:01 +0000 (12:51 -0700)
committerDaniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Wed, 20 Mar 2024 21:40:57 +0000 (14:40 -0700)
commit4c15a6dcee20951ea619eca26e249f8f13275224
tree5a8ca77c399917618dbc0e1fcba29c01cd7df53b
parent649a125a88da64a66b0836cb7998bb433bbf1bf5
drm/xe/uc: Use u64 for offsets for which we use upper_32_bits()

The GGTT is currently a 32 bit address space, but the HW and GuC
support 48b addresses in GGTT-related operations, both to keep the
interface/HW paths common between PPGTT and GGTT and to allow for
future increase of the GGTT size.
This leaves us having to program a 64b field with a 32b offset, which
currently we're in some cases doing this by using an upper_32_bits()
call on a 32b variable, which doesn't make any sense. To do this cleanly
we have 2 options:

1 - Set the upper 32 bits directly to zero.
2 - Use 64b variables for the offset and keep programming the whole thing,
    so we're ready if we ever have bigger offsets.

This patch goes with option #2 and switches the related variables to u64.

v2: don't change the log ctl flag variable (John)

Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: John Harrison <John.C.Harrison@Intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240319195101.2784480-1-daniele.ceraolospurio@intel.com
drivers/gpu/drm/xe/xe_guc_hwconfig.c
drivers/gpu/drm/xe/xe_guc_submit.c
drivers/gpu/drm/xe/xe_uc_fw.c