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(parent: c61e4e7) | patch
clk: tegra: Fix enabling of PLLE
authorThierry Reding <treding@nvidia.com>
Fri, 4 Apr 2014 13:55:15 +0000 (15:55 +0200)
committerPeter De Schrijver <pdeschrijver@nvidia.com>
Thu, 17 Apr 2014 11:12:46 +0000 (14:12 +0300)
commit4ccc402ece35695dd2884ec0b652d52ae0230f13
treee72273317bd892e4678ee6ccf776831e863554a1tree | snapshot
parentc61e4e75b95bda4c6fec134aa9f08b5629b532e6commit | diff
clk: tegra: Fix enabling of PLLE

When enabling the PLLE as its final step, clk_plle_enable() would
accidentally OR in the value previously written to the PLLE_SS_CTRL
register.

Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/clk/tegra/clk-pll.c diff | blob | history
ep93xx device tree rework repo: git://git.maquefel.me/linux.git