target/riscv: Convert to 3-phase reset
authorPeter Maydell <peter.maydell@linaro.org>
Thu, 24 Nov 2022 11:50:17 +0000 (11:50 +0000)
committerPeter Maydell <peter.maydell@linaro.org>
Fri, 16 Dec 2022 15:58:15 +0000 (15:58 +0000)
commit4fa485a78e7e887afccdd183602cfb117cf05659
tree84802a9492b3784bc433314447925e779557fd8e
parenta1c5d644b77b9e5c2639e7c7a6257398d72fc81d
target/riscv: Convert to 3-phase reset

Convert the riscv CPU class to use 3-phase reset, so it doesn't
need to use device_class_set_parent_reset() any more.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com>
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Greg Kurz <groug@kaod.org>
Message-id: 20221124115023.2437291-15-peter.maydell@linaro.org
target/riscv/cpu.c
target/riscv/cpu.h