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(parent: e70aa16) | patch
target/riscv: rvv-1.0: mask-register logical instructions
authorFrank Chang <frank.chang@sifive.com>
Fri, 10 Dec 2021 07:56:35 +0000 (15:56 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Mon, 20 Dec 2021 04:51:36 +0000 (14:51 +1000)
commit50f6696c0f87372348b0760f858187cda3e7eb7f
tree80ef3667e87e4a41f91811a6c8e88810f198a484tree | snapshot
parente70aa16e5e506475459cd524449e39484b4a984fcommit | diff
target/riscv: rvv-1.0: mask-register logical instructions

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211210075704.23951-50-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/insn_trans/trans_rvv.c.inc diff | blob | history
target/riscv/vector_helper.c diff | blob | history
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