RISC-V: Add support for the Zifencei extension
authorPalmer Dabbelt <palmer@sifive.com>
Mon, 24 Jun 2019 08:59:05 +0000 (01:59 -0700)
committerPalmer Dabbelt <palmer@sifive.com>
Wed, 26 Jun 2019 05:31:21 +0000 (22:31 -0700)
commit50fba816cd226001bec3e495c39879deb2fa5432
tree0a8b056c8e90559d6a59fe53c53a8607617c08e4
parent0a13a5b856ebb59dec6d165b87a0ba0e1e2dd952
RISC-V: Add support for the Zifencei extension

fence.i has been split out of the base ISA as part of the ratification
process.  This patch adds a Zifencei argument, which disables the
fence.i instruction.

Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.c
target/riscv/cpu.h
target/riscv/insn_trans/trans_rvi.inc.c
target/riscv/translate.c