target/riscv: Add properties for Indirect CSR Access extension
authorKaiwen Xue <kaiwenx@rivosinc.com>
Fri, 10 Jan 2025 08:21:29 +0000 (00:21 -0800)
committerAlistair Francis <alistair.francis@wdc.com>
Sat, 18 Jan 2025 23:44:35 +0000 (09:44 +1000)
commit51c4f3e982daa1d2fffa63e0b73565c948d26d2b
tree2be540dffb9f00627d8cde92f2b1cd6b4d06292e
parentcb938a0a24bc911894b6fec1429e2e0cc8b2f948
target/riscv: Add properties for Indirect CSR Access extension

This adds the properties for sxcsrind. Definitions of new registers and
implementations will come with future patches.

Signed-off-by: Kaiwen Xue <kaiwenx@rivosinc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-ID: <20250110-counter_delegation-v5-1-e83d797ae294@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.c
target/riscv/cpu_cfg.h